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In computing, x86 virtualization refers to hardware virtualization for the x86 architecture. It allows multiple operating systems to simultaneously share x86 processor resources in a safe and efficient manner.
In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of virtualization support while attaining reasonable performance. In 2006, both Intel (VT-x) and AMD (AMD-V) introduced limited hardware virtualization support that allowed for simpler virtualization software but offered very little speed benefits. Greater hardware support, that allowed for substantial speed improvements, came with later processor models.
1 Software-based virtualization,
2 Hardware assist
2.1.1 AMD virtualization (AMD-V) ,
2.1.2 Intel virtualization (VT-x),
2.1.3 VIA virtualization (VIA VT),
2.1.4 Software using AMD-V and/or Intel VT,
2.2.1 I/O MMU virtualization (AMD-Vi and VT-d),
2.2.2 Network virtualization (VT-c),
2.2.3 PCI-SIG I/O virtualization (IOV),
3 See also,
5 External links,
The following discussion focuses only on virtualization of protected mode of the x86 architecture.
In protected mode the operating system kernel runs at a higher privilege such as ring 0, and applications at a lower privilege such as ring 3. In software-based virtualization, a host OS has direct access to hardware while the guest OSs have limited access to hardware, just like any other application of the host OS. One approach used in x86 software-based virtualization to overcome this limitation is called ring deprivileging, in which involves running the guest OS at a ring higher than 0.
Three techniques made virtualization of protected mode possible:
Binary translation is used to rewrite in terms of ring 3 instructions certain ring 0 instructions, such as POPF, that would otherwise fail silently or behave differently when executed above ring 0, making the classic trap-and-emulate virtualization impossible. To improve performance, the translated basic blocks need to be cached in a coherent way that detects code patching (used in VxDs for instance), the reuse of pages by the guest OS, or even self-modifying code.,
A number of key data structures used by a processor need to be shadowed. Because most operating systems use paged virtual memory, and granting the guest OS direct access to the MMU would mean loss of control by the virtualization manager, some of the work of the x86 MMU needs to be duplicated in software for the guest OS using a technique known as shadow page tables. This involves denying the guest OS any access to the actual page table entries by trapping access attempts and emulating them instead in software. The x86 architecture uses hidden state to store segment descriptors in the processor, so once the segment descriptors have been loaded into the processor, the memory from which they have been loaded may be overwritten and there is no way to get the descriptors back from the processor. Shadow descriptor tables must therefore be used to track changes made to the descriptor tables by the guest OS.,
I/O device emulation: Unsupported devices on the guest OS must be emulated by a device emulator that runs in the host OS.,
These techniques incur some performance overhead due to lack of MMU virtualization support, as compared to a VM running on a natively virtualizable architecture such as the IBM System/370.
On traditional mainframes, the classic type 1 hypervisor was self-standing and did not depend on any operating system or run any user applications itself. In contrast, the first x86 virtualization products were aimed at workstation computers, and ran a guest OS inside a host OS by embedding the hypervisor in a kernel module that ran under the host OS (type 2 hypervisor).
There has been some controversy whether the x86 architecture with no hardware assistance is virtualizable as described by Popek and Goldberg. VMware researchers pointed out in a 2006 ASPLOS paper that the above techniques made the x86 platform virtualizable in the sense of meeting the three criteria of Popek and Goldberg, albeit not by the classic trap-and-emulate technique.
A different route was taken by other systems like Denali, L4, and Xen, known as paravirtualization, which involves porting operating systems to run on the resulting virtual machine, which does not implement the parts of the actual x86 instruction set that are hard to virtualize. The paravirtualized I/O has significant performance benefits as demonstrated in the original SOSP'03 Xen paper.
The initial version of x86-64 (AMD64) did not allow for a software-only full virtualization due to the lack of segmentation support in long mode, which made the protection of the hypervisor's memory impossible, in particular, the protection of the trap handler that runs in the guest kernel address space. Revision D and later 64-bit AMD processors (as a rule of thumb, those manufactured in 90 nm or less) added basic support for segmentation in long mode, making it possible to run 64-bit guests in 64-bit hosts via binary translation. Intel did not add segmentation support to its x86-64 implementation (Intel 64), making 64-bit software-only virtualization impossible on Intel CPUs, but Intel VT-x support makes 64-bit hardware assisted virtualization possible on the Intel platform.
On some platforms, it is possible to run a 64-bit guest on a 32-bit host OS if the underlying processor is 64-bit and supports the necessary virtualization extensions.
In 2005 and 2006, Intel and AMD (working independently) created new processor extensions to the x86 architecture. The first generation of x86 hardware virtualization addressed the issue of privileged instructions. The issue of low performance of virtualized system memory was addressed with MMU virtualization that was added to the chipset later.
AMD virtualization (AMD-V) :
AMD developed its first generation virtualization extensions under the code name "Pacifica", and initially published them as AMD Secure Virtual Machine (SVM), but later marketed them under the trademark AMD Virtualization, abbreviated AMD-V.
On May 23, 2006, AMD released the Athlon 64 ("Orleans"), the Athlon 64 X2 ("Windsor") and the Athlon 64 FX ("Windsor") as the first AMD processors to support this technology.
AMD-V capability also features on the Athlon 64 and Athlon 64 X2 family of processors with revisions "F" or "G" on socket AM2, Turion 64 X2, and Opteron 2nd generation and 3rd-generation,Phenom and Phenom II processors. The APU Fusion processors support AMD-V. AMD-V is not supported by any Socket 939 processors. The only Sempron processors which support it are Huron and Sargas.
AMD Opteron CPUs beginning with the Family 0x10 Barcelona line, and Phenom II CPUs, support a second generation hardware virtualization technology called Rapid Virtualization Indexing (formerly known as Nested Page Tables during its development), later adopted by Intel as Extended Page Tables (EPT).
The CPU flag for AMD-V is "svm". This may be checked in BSD derivatives via dmesg or sysctl and in Linux via /proc/cpuinfo.
Intel virtualization (VT-x):
"Intel VT-x" redirects here. It is not to be confused with Intel VT-i.
Previously codenamed "Vanderpool", VT-x represents Intel's technology for virtualization on the x86 platform.
On November 13, 2005, Intel released two models of Pentium 4 (Model 662 and 672) as the first Intel processors to support VT-x.
As of 2009 not all Intel processors supported VT-x, which Intel uses to segment its market. Support for VT-x may even vary between different versions (as identified by Intel's sSpec Number) of the same model number. For a complete and up-to-date list see the Intel website. Even in May, 2011, the Intel CPU P6100 which is in laptops does not support hardware virtualization.
With some motherboards, Intel's VT-x feature must be enabled in the BIOS before applications can make use of it.
Intel started to include Extended Page Tables (EPT), a technology for page-table virtualization, since the Nehalem architecture.
Intel started to include VMCS Shadowing, a technology to accelerate nested virtualization of VMMs, since the Haswell architecture.
The CPU flag for VT-x is "vmx". This may be checked in Linux via /proc/cpuinfo or in Mac OS X via sysctl machdep.cpu.features.
VIA virtualization (VIA VT):
VIA Nano 3000 Series Processors and higher support a so-called VIA VT virtualization technology compatible with Intel VT.
Software using AMD-V and/or Intel VT:
Main article: http://en.wikipedia.org/wiki/Comparison_of_platform_virtual_machines
Main article: http://en.wikipedia.org/wiki/I/O_virtualization
Memory and I/O virtualization is performed by the chipset. Typically these features must be enabled by the BIOS, which must be able to support them and also be set to use them.
I/O MMU virtualization (AMD-Vi and VT-d):
Main article: http://en.wikipedia.org/wiki/IOMMU#Virtualization
An input/output memory management unit (IOMMU) enables guest virtual machines to directly use peripheral devices, such as Ethernet, accelerated graphics cards, and hard-drive controllers, through DMA and interrupt remapping. This is sometimes called PCI passthrough. Both AMD and Intel have released specifications:
AMD's I/O Virtualization Technology, "AMD-Vi", originally called "IOMMU".,
Intel's "Virtualization Technology for Directed I/O" (VT-d). Included in most but not all Nehalem-based processors.,
Network virtualization (VT-c):
Intel's "Virtualization Technology for Connectivity" (VT-c).,
PCI-SIG I/O virtualization (IOV):
PCI-SIG I/O virtualization (IOV) provides a set of general (non-x86 specific) I/O virtualization methods based on PCI Express (PCIe) native hardware, as standardized by PCI-SIG:
Address translation services (ATS)
this supports native IOV across PCI Express via address translation. It requires support for new transactions to configure such translations.
Single-root IOV (SR-IOV or SRIOV)
this supports native IOV in existing single-root complex PCI Express topologies. It requires support for new device capabilities to configure multiple virtualized configuration spaces.
Multi-root IOV (MR-IOV)
this supports native IOV in new topologies (e.g., blade servers) by building on SR-IOV to provide multiple root complexes which share a common PCI Express hierarchy.
In SR-IOV, the most common of these, a host VMM configures supported devices to create and allocate virtual "shadows" of their configuration spaces so that virtual machine guests can directly configure and access such "shadow" device resources.